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1 description the cat5221 is two digitally programmable potentiometers (dpps) integrated with control logic and 16 bytes of nvram memory. each dpp consists of a series of 63 resistive elements connected between two externally accessible end points. the tap points between each resistive element are connected to the wiper outputs with cmos switches. a separate 6-bit control register (wcr) independently controls the wiper tap switches for each dpp. associated with each wiper control register are four 6-bit non-volatile memory data registers (dr) used for storing up to four wiper settings. writing to the wiper control register or any of the non-volatile data cat5221 dual digitally programmable potentiometers (dpp?) with 64 taps and 2-wire interface features two linear-taper digitally programmable potentiometers 64 resistor taps per potentiometer end to end resistance 2.5k ? , 10k ? , 50k ? or 100k ? potentiometer control and memory access via 2-wire interface (i 2 c like) low wiper resistance, typically 80 ? ? ? ? ? nonvolatile memory storage for up to four wiper settings for each potentiometer automatic recall of saved wiper settings at power up 2.5 to 6.0 volt operation standby current less than 1 a 1,000,000 nonvolatile write cycles 100 year nonvolatile memory data retention 20-lead soic and tssop packages commercial and industrial temperature ranges pin configuration functional diagram ?2004 by catalyst semiconductor, inc. characteristics subject to change without notice advance information document no. 2113, rev. g registers is via a 2-wire serial bus (i 2 c-like). on power- up, the contents of the first data register (dr0) for each of the four potentiometers is automatically loaded into its respective wiper control register (wcr). the cat5221 can be used as a potentiometer or as a two terminal, variable resistor. it is intended for circuit level or system level adjustments in a wide variety of applications. it is available in the 0 c to 70 c commercial and -40 c to 85 c industrial operating temperature ranges and offered in a 20-lead soic package. h a l o g e n f r e e tm l e a d f r e e w1 w0 h0 h1 r r l0 l1 r r wiper control registers nonvolatile data registers 2-wire bus interface control logic scl sda a0 a1 a2 a3 r r 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 cat 5221 r w0 r l0 r h0 a 0 a 2 r w1 r l1 rh 1 sda gnd v cc nc nc nc a 1 a 3 scl nc nc nc soic package (j, w) tssop package (u, y)
2 cat5221 document no. 2113, rev. g advance information pin description pin (soic)name function 1r w0 wiper terminal for potentiometer 0 2r l0 low reference terminal for potentiometer 0 3r h0 high reference terminal for potentiometer 0 4 a0 device address, lsb 5 a2 device address 6r w1 wiper terminal for potentiometer 1 7r l1 low reference terminal for potentiometer 1 8r h1 high reference terminal for potentiometer 1 9 sda serial data input/output 10 gnd ground 11 nc no connect 12 nc no connect 13 nc no connect 14 scl bus serial clock 15 a3 device address 16 a1 device address 17 nc no connect 18 nc no connect 19 nc no connect 20 vcc supply voltage pin descriptions scl: serial clock the cat5221 serial clock input pin is used to clock all data transfers into or out of the device. sda: serial data the cat5221 bidirectional serial data pin is used to transfer data into and out of the device. the sda pin is an open drain output and can be wire- ored with the other open drain or open collector outputs. a0, a1, a2, a3: device address inputs these inputs set the device address when ad- dressing multiple devices. when these pins are left floating the default values are zero. a total of sixteen devices can be addressed on a single bus. a match in the slave address must be made with the address input in order to initiate communication with the cat5221. r h , r l : resistor end points the two sets of r h and r l pins are equivalent to the terminal connections on a mechanical potenti- ometer. r w : wiper the two r w pins are equivalent to the wiper terminal of a mechanical potentiometer. device operation the cat5221 is two resistor arrays integrated with 2- wire serial interface logic, two 6-bit wiper control registers and eight 6-bit, non-volatile memory data registers. each resistor array contains 63 separate resistive elements connected in series. the physical ends of each array are equivalent to the fixed terminals of a mechanical potentiometer (r h and r l ). r h and r l are symmetrical and may be interchanged. the tap positions between and at the ends of the series resistors are connected to the output wiper terminals (r w ) by a cmos transistor switch. only one tap point for each potentiometer is connected to its wiper terminal at a time and is determined by the value of the wiper control register. data can be read or written to the wiper control registers or the non-volatile memory data registers via the 2-wire bus. additional instructions allows data to be transferred between the wiper control registers and each respective potentiometer's non-volatile data registers. also, the device can be instructed to operate in an "increment/decrement" mode.
3 cat5221 document no. 2113, rev. g advance information potentiometer characteristics over recommended operating conditions unless otherwise stated. symbol parameter test conditions min typ max units r pot potentiometer resistance (-00 ) 100 k ? r pot potentiometer resistance (-50 ) 50 k ? r pot potentiometer resistance (-10 ) 10 k ? r pot potentiometer resistance (-2.5 ) 2.5 k ? potentiometer resistance +20 % tolerance r pot matching 1 % power rating 25 c, each pot 50 mw i w wiper current +6 ma r w wiper resistance i w = +3ma @ v cc =3v 300 ? r w wiper resistance i w = +3ma @ v cc = 5v 80 150 ? v term voltage on any r h or r l pin v ss = 0v gnd v cc v v n noise tbd nv/ hz resolution 1.6 % absolute linearity (3) r w(n)(actual) -r (n)(expected) (6) +1 lsb (5) relative linearity (4) r w(n+1) -[r w(n)+lsb ] (6) +0.2 lsb (5) temperature coefficient of +300 ppm/ c tc rpot r pot tc ratio ratiometric temp. coefficient 20 ppm/ c c h /c l /c w potentiometer capacitances 10/10/25 pf r iso isolation resistance tbd ? fc frequency response r pot = 50k ? 0.4 mhz absolute maximum ratings* temperature under bias .................. -55 c to +125 c storage temperature ........................ -65 c to +150 c voltage on any pin with respect tov ss (1) .................... -2.0v to +v cc +2.0v v cc with respect to ground ................ -2.0v to +7.0v package power dissipation capability (t a = 25 c) ................................... 1.0w lead soldering temperature (10 secs) ............ 300 c wiper current .................................................. +12ma note: (1) the minimum dc input voltage is 0.5v. during transitions, inputs may undershoot to 2.0v for periods of less than 20 ns. maximum dc voltage on output pins is v cc +0.5v, which may overshoot to v cc +2.0v for periods of less than 20 ns. *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. exposure to any absolute maximum rating for extended periods may affect device perfor- mance and reliability. note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) latch-up protection is provided for stresses up to 100 ma on address and data pins from 1v to v cc +1v. (3) absolute linearity is utilitzed to determine actual wiper voltage versus expected voltage as determined by wiper position wh en used as a potentiometer. (4) relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. it is a measure of the error in step size. (5) mi = r tot / 63 or (r h - r l ) / 63, single pot (6) n = 0, 1, 2, ..., 63 recommended operating conditions: v cc = +2.5v to +6.0v temperature min max commercial 0 c70 c industrial -40 c85 c
4 cat5221 document no. 2113, rev. g advance information symbol parameter min typ max units f scl clock frequency 400 khz t i (1) noise suppression time constant at scl, sda inputs 50 ns t aa slc low to sda data out and ack out 0.9 s t buf (1) time the bus must be free before a new 1.2 s transmission can start t hd:sta start condition hold time 0.6 s t low clock low period 1.2 s t high clock high period 0.6 s t su:sta start condition setuptime (for a repeated start condition) 0.6 s t hd:dat data in hold time 0 ns t su:dat data in setup time 100 ns t r (1) sda and scl rise time 0.3 s t f (1) sda and scl fall time 300 ns t su:sto stop condition setup time 0.6 s t dh data out hold time 50 ns note: (1) this parameter is tested initially and after a design or process change that affects the parameter. capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v symbol test conditions min typ max units c i/o (1) input/output capacitance (sda) v i/o = 0v 8 pf c in (1) input capacitance (a0, a1, a2, a3, scl) v in = 0v 6 pf power up timing (1) over recommended operating conditions unless otherwise stated. symbol parameter min typ max units t pur power-up to read operation 1 ms t puw power-up to write operation 1 ms d.c. operating characteristics over recommended operating conditions unless otherwise stated. symbol parameter test conditions min typ max units i cc power supply current f scl = 400khz 1 ma i sb standby current (v cc = 5.0v) v in = gnd or v cc; sda open 1 a i li input leakage current v in = gnd to v cc 10 a i lo output leakage current v out = gnd to v cc 10 a v il input low voltage -1 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 1.0 v v ol1 output low voltage (v cc = 3.0v) i ol = 3 ma 0.4 v a.c. characteristics over recommended operating conditions unless otherwise stated.
5 cat5221 document no. 2113, rev. g advance information t high scl sda in sda out t low t f t low t r t buf t su:sto t su:dat t hd:dat t hd:sta t su:sta t aa t dh figure 1. bus timing t wr stop condition start condition address ack 8th bit byte n scl sda figure 2. write cycle timing start bit sda stop bit scl figure 3. start/stop timing note: (1) this parameter is tested initially and after a design or process change that affects the parameter. (2) t pur and t puw are the delays required from the time v cc is stable until the specified operation can be initiated. write cycle limits over recommended operating conditions unless otherwise stated. symbol parameter min typ max units t wr write cycle time 5 ms the write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. dur ing the write cycle, the bus interface circuits are disabled, sda is allowed to remain high, and the device does not respond to its slave address. reliability characteristics over recommended operating conditions unless otherwise stated. symbol parameter reference test method min typ max units n end (1) endurance mil-std-883, test method 1033 1,000,000 cycles/byte t dr (1) data retention mil-std-883, test method 1008 100 years v zap (1) esd susceptibility mil-std-883, test method 3015 2000 volts i lth (1)(2) latch-up jedec standard 17 100 ma
6 cat5221 document no. 2113, rev. g advance information serial bus protocol the following defines the features of the 2-wire bus protocol: (1) data transfer may be initiated only when the bus is not busy. (2) during a data transfer, the data line must remain stable whenever the clock line is high. any changes in the data line while the clock is high will be interpreted as a start or stop condition. the device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the cat5221 will be considered a slave device in all applications. start condition the start condition precedes all commands to the device, and is defined as a high to low transition of sda when scl is high. the cat5221 monitors the sda and scl lines and will not respond until this condition is met. stop condition a low to high transition of sda when scl is high determines the stop condition. all operations must end with a stop condition. device addressing the bus master begins a transmission by sending a start condition. the master then sends the address of the particular slave device it is requesting. the four most significant bits of the 8-bit slave address are fixed as 0101 for the cat5221 (see figure 5). the next four significant bits (a3, a2, a1, a0) are the device address bits and define which device the master is accessing. up to sixteen devices may be individually addressed by the system. typically, +5v and ground are hard-wired to these pins to establish the device's address. after the master sends a start condition and the slave address byte, the cat5221 monitors the bus and responds with an acknowledge (on the sda line) when its address matches the transmitted slave address. acknowledge after a successful data transfer, each receiving device is required to generate an acknowledge. the acknowledging device pulls down the sda line during the ninth clock cycle, signaling that it received the 8 bits of data. the cat5221 responds with an acknowledge after receiving a start condition and its slave address. if the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. when the cat5221 is in a read mode it transmits 8 bits of data, releases the sda line, and monitors the line for an acknowledge. once it receives this acknowledge, the cat5221 will continue to transmit data. if no acknowledge is sent by the master, the device terminates data transmission and waits for a stop condition. acknowledge 1 start scl from master 89 data output from transmitter data output from receiver figure 4. acknowledge timing 5020 fhd f06
7 cat5221 document no. 2113, rev. g advance information write operations in the write mode, the master device sends the start condition and the slave address information to the slave device. after the slave generates an acknowledge, the master sends the instruction byte that defines the requested operation of cat5221. the instruction byte consist of a four-bit opcode followed by two register selection bits and two pot selection bits. after receiving another acknowledge from the slave, the master device transmits the data to be written into the selected register. the cat5221 acknowledges once more and the master generates the stop condition, at which time if a non- volatile data register is being selected, the device begins an internal programming cycle to non-volatile memory. while this internal cycle is in progress, the device will not respond to any request from the master device. acknowledge polling the disabling of the inputs can be used to take advantage of the typical write cycle time. once the stop condition is issued to indicate the end of the host's write operation, the cat5221 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address. if the cat5221 is still busy with the write operation, no ack will be returned. if the cat5221 has completed the write operation, an ack will be returned and the host can then proceed with the next instruction operation. figure 6. write timing figure 5. slave address bits 0 1 0 1 a3 a2 a1 a0 cat5221 * a0, a1, a2 and a3 correspond to pin a0, a1, a2 and a3 of the device. ** a0, a1, a2 and a3 must compare to its corresponding hard wired input pins. 5020 fhd f08 s a c k a c k dr wcrdata s t o p p bus activity: master sda line s t a r t a c k slave/dpp address instruction byte fixed variable op code data register address pot/wcr address
8 cat5221 document no. 2113, rev. g advance information instruction and register description instructions slave address byte the first byte sent to the cat5221 from the master/ processor is called the slave/dpp address byte. the most significant four bits of the slave address are a device type identifier. these bits for the cat5221 are fixed at 0101[b] (refer to table 1). the next four bits, a3 - a0, are the internal slave address and must match the physical device address which is defined by the state of the a3 - a0 input pins for the cat5221 to successfully continue the command sequence. only the device which slave address matches the incoming device address sent by the master executes the instruction. the a3 - a0 inputs can be actively driven by cmos input signals or tied to v cc or v ss . instruction byte the next byte sent to the cat5221 contains the instruction and register pointer information. the four most significant bits used provide the instruction opcode i [3:0]. the p0 bit points to one of the wiper control registers. the least two significant bits, r1 and r0, point to one of the four data registers of each associated potentiometer. the format is shown in table 2. table 1. identification byte format id3 id2 id1 id0 a3 a2 a1 a0 0101 (msb) (lsb) device type identifier slave address table 2. instruction byte format data register selected r1 r0 dr0 0 0 dr1 0 1 dr2 1 0 dr3 1 1 data register selection i3 i2 i1 i0 r1 r0 0p0 (msb) (lsb) instruction data register wcr/pot selection opcode selection
9 cat5221 document no. 2113, rev. g advance information table 3. instruction set wiper control and data registers wiper control register (wcr) the cat5221 contains two 6-bit wiper control registers, one for each potentiometer. the wiper control register output is decoded to select one of 64 switches along its resistor array. the contents of the wcr can be altered in four ways: it may be written by the host via write wiper control register instruction; it may be written by transferring the contents of one of four associated data registers via the xfr data register instruction, it can be modified one step at a time by the increment/decrement instruction (see instruction section for more details). finally, it is loaded with the content of its data register zero (dr0) upon power-up. the wiper control register is a volatile register that loses its contents when the cat5221 is powered-down. although the register is automatically loaded with the value in dr0 upon power-up, this may be different from the value present at power-down. data registers (dr) each potentiometer has four 6-bit non-volatile data registers. these can be read or written directly by the host. data can also be transferred between any of the four data registers and the associated wiper control register. any data changes in one of the data registers is a non-volatile operation and will take a maximum of 5ms. if the application does not require storage of multiple settings for the potentiometer, the data registers can be used as standard memory locations for system parameters or user preference data. instructions four of the nine instructions are three bytes in length. these instructions are: read wiper control register - read the current wiper position of the selected potentiometer in the wcr write wiper control register - change current wiper position in the wcr of the selected potentiometer read data register - read the contents of the selected data register write data register - write a new value to the selected data register the basic sequence of the three byte instructions is illustrated in figure 8. these three-byte instructions note: 1/0 = data is one or zero instruction instruction set operation i3 i2 i1 i0 r1 r0 read wiper control register 1001 0 0 r ead the contents of the wiper control register pointed to by p0 write wiper control register 1010 0 0 w rite new value to the wiper control register pointed to by p0 read data register 1011 1/01/0r ead the contents of the data register pointed to by p0 and r1-r0 write data register 1100 1/01/0w rite new value to the data register pointed to by p0 and r1-r0 xfr data register to wiper control register 1101 1/01/0 transfer the contents of the data register pointed to by p0 and r1-r0 to its associated w iper c ontrol r egister xfr wiper control register to data register 1110 1/01/0 transfer the contents of the wiper control register pointed to by p0 to the data register pointed to by r1-r0 global xfr data registers to wiper control registers 0001 1/01/0 transfer the contents of the data registers pointed to by r1-r0 of all four pots to their respective wiper control register s global xfr wiper control registers to data register 1000 1/01/0 transfer the contents of both wiper control registers to their respective data registers pointed to by r1-r0 of all four pots increment/decrement wiper control register 0010 0 0 enable increment/decrement of the c ontrol latch pointed to by p0 1/0 1/0 1/0 1/0 1/0 1/0 00 00 1/0 wcr0/ p0 0 0 0 0 0 0 0 0
10 cat5221 document no. 2113, rev. g advance information exchange data between the wcr and one of the data registers. the wcr controls the position of the wiper. the response of the wiper to this action will be delayed by t wrl . a transfer from the wcr (current wiper position), to a data register is a write to non-volatile memory and takes a minimum of t wr to complete. the transfer can occur between one of the four potentiometers and one of its associated registers; or the transfer can occur between all potentiometers and one associated register. four instructions require a two-byte sequence to complete, as illustrated in figure 7. these instructions transfer data between the host/processor and the cat5221; either between the host and one of the data registers or directly between the host and the wiper control register. these instructions are: xfr data register to wiper control register this transfers the contents of one specified data register to the associated wiper control register. xfr wiper control register to data register this transfers the contents of the specified wiper control register to the specified associated data register. global xfr data register to wiper control register this transfers the contents of all specified data registers to the associated wiper control registers. global xfr wiper counter register to data register this transfers the contents of all wiper control registers to the specified associated data registers. increment/decrement command the final command is increment/decrement (figure 5 and 9). the increment/decrement command is different from the other commands. once the command is issued and the cat5221 has responded with an acknowledge, the master can clock the selected wiper up and/or down in one segment steps; thereby providing a fine tuning capability to the host. for each scl clock pulse (t high ) while sda is high, the selected wiper will move one resistor segment towards the r h terminal. similarly, for each scl clock pulse while sda is low, the selected wiper will move one resistor segment towards the r l terminal. see instructions format for more detail. figure 7. two-byte instruction sequence figure 8. three-byte instruction sequence figure 9. increment/decrement instruction sequence s t a r t 0101 a2 a0 a c k i2 i1 i0 r1 r0 a c k sda s t o p id3 id2 id1 id0 device id internal instruction opcode address register address 0 p0 pot/wcr address a1 a3 i3 i3 i2 i1 i0 id3 id2 id1 id0 device id internal instruction opcode address data register address s t a r t 0101 a2 a1 a0 a c k r0 pot/wcr address 0p0 a c k sda s t o p i n c 1 i n c 2 i n c n d e c 1 d e c n r1 a3 i3 i2 i1 i0 r1 r0 id3 id2 id1 id0 device id internal instruction opcode address data register address wcr[7:0] or data register d[7:0] s t a r t 0 101 a2 a1 a0 a c k pot/wcr address 0p0 a c k sda s t o p a c k d7 d6 d5 d4 d3 d2 d1 d0 a3
11 cat5221 document no. 2113, rev. g advance information figure 10. increment/decrement timing limits scl sda r w inc/dec command issued voltage out t wrid instruction format read wiper control register (wcr) write wiper control register (wcr) read data register (dr) write data register (dr) device addresses instruction data 0 1 0 1 a3a2a1a0 1 0 0 1 0 p0 0 0 7 6 5 4 3 2 1 0 s t a r t a c k a c k a c k s t o p device addresses instruction data 0 1 0 1 a3 a2 a1 a0 1 0 1 1 0 p0 r1 r0 7 6 5 4 3 2 1 0 s t a r t a c k a c k a c k s t o p device addresses instruction data 0 1 0 1 a3 a2 a1 a0 1 1 0 0 0 p0 r1 r0 7 6 5 4 3 2 1 0 s t a r t a c k a c k a c k s t o p device addresses instruction data 0 1 0 1 a3a2a1a0 1 0 1 0 0 p0 0 0 7 6 5 4 3 2 1 0 s t a r t a c k a c k a c k s t o p
12 cat5221 document no. 2113, rev. g advance information notes: (1) any write or transfer to the non-volatile data registers is followed by a high voltage cycle after a stop has been issued. device address instruction 0 1 0 1 a3 a2 a1 a0 1 1 0 1 0 p0 r1r0 device address instruction 0 1 0 1 a3 a2 a1 a0 1 0 0 0 0 0 r1 r0 global transfer wiper control register (wcr) to data register (dr) instruction format (continued) transfer wiper control register (wcr) to data register (dr) transfer data register (dr) to wiper control register (wcr) s t a r t a c k a c k s t o p increment (i)/decrement (d) wiper control register (wcr) global transfer data register (dr) to wiper control register (wcr) a c k a c k s t o p s t a r t device address instruction 0 1 0 1a3a2a1a0 0 0 0 1 00r1r0 a c k a c k s t o p s t a r t device address instruction 0 1 0 1 a3 a2 a1 a0 1 1 1 0 0 p0 r1r0 a c k a c k s t o p s t a r t device address instruction data 0 1 0 1 a3 a2 a1 a0 0 0 1 0 0 p0 0 0 i/d i/d i/d i/d s t a r t a c k a c k a c k s t o p
13 cat5221 document no. 2113, rev. g advance information 5221 5221 package j: soic u: tssop w: soic (lead free, halogen free) y: tssop (lead free, halogen free) notes: (1) the device used in the above example is a cat5221ji-10-te13 (soic, industrial temperature, 10kohm, tape & reel) ordering information
14 cat5221 document no. 2113, rev. g advance information 20-lead 300 mil wide soic (j, w) 0.2914 (7.40) 0.2992 (7.60) 0.394 (10.00) 0.419 (10.65) 0.0926 (2.35) 0.1043 (2.65) 0.0040 (0.10) 0.0118 (0.30) 0.050 (1.27) bsc 0.013 (0.33) 0.020 (0.51) 0 8 0.0091 (0.23) 0.0125 (0.32) 0.010 (0.25) 0.029 (0.75) x 45 0.016 (0.40) 0.050 (1.27) 0.5985 (15.20) 0.6141 (15.60) packaging information
15 cat5221 document no. 2113, rev. g advance information 20-lead tssop (u, y) 7.72 typ 4.16 typ (1.78 typ) 0.42 typ 0.65 typ land p a ttern recommend a tion -a- -b- 3.2 6.4 a b c 0.2 8 5 3.0 + 0.1 4.4 + 0.1 all lead tips pin #1 ident. 1 4 all lead tips 1.1 max typ 0.1 c (0.9) 0.10 + 0.05 typ 0.19 - 0.30 typ 0.3 m a b s c s 0.65 typ see detail a 0.09 - 0.20 typ 0.6+0.1 seating plane gage plane 0.25 0 o - 8 o detail a -c- notes: (1) lead coplanarity is 0.004" (0.102mm) maximum.
date rev. reason 9/30/2003 e deleted wp from functional diagram, pg. 1 10/1/2003 f changed designation to advance 3/10/2004 g added tssop package in all areas catalyst semiconductor, inc. corporate headquarters 1250 borregas avenue sunnyvale, ca 94089 phone: 408.542.1000 fax: 408.542.1200 www.catalyst-semiconductor.com publication #: 2113 revison: g issue date: 3/10/04 type: advance copyrights, trademarks and patents trademarks and registered trademarks of catalyst semiconductor include each of the following: dpp dpps ae 2 i 2 c is a trademark of philips corporation catalyst semiconductor has been issued u.s. and foreign patents and has patent applications pending that protect its products. for a complete list of patents issued to catalyst semiconductor contact the companys corporate office at 408.542.1000. catalyst semiconductor makes no warranty, representation or guarantee, express or implied, regarding the suitability of its products for any particular purpose, nor that the use of its products will not infringe its intellectual property rights or the rights of third parties with respect to any particular use or application and specifically disclaims any and all liability aris ing out of any such use or application, including but not limited to, consequential or incidental damages. catalyst semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgica l implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the catalyst semic onductor product could create a situation where personal injury or death may occur. catalyst semiconductor reserves the right to make changes to or discontinue any product or service described herein without not ice. products with data sheets labeled "advance information" or "preliminary" and other products described herein may not be in production or offered for sale . catalyst semiconductor advises customers to obtain the current version of the relevant product information before placing order s. circuit diagrams illustrate typical semiconductor applications and may not be complete. revision history

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